Re: [myhdl-list] Control over output file generation
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From: Jan D. <ja...@ja...> - 2009-01-31 10:37:26
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Günter Dannoritzer wrote: > Eric Jonas wrote: >> Hello! MyHDL has been a lot of fun thus far, but as I look toward >> automating more of my design flow, I'm stuck on one question: The >> correct way to control both the location and name of the generated >> verilog/vhdl code. > > The file name in connection with the module name can be changed with the > toVerilog.name or toVHDL.name attribute. See the reference document for > that: > > http://www.myhdl.org/doc/0.6/manual/reference.html#myhdl.toVerilog > http://www.myhdl.org/doc/0.6/whatsnew/0.6.html#toVHDL > > Now I am not sure whether that would also allow to add a path. You might > have to do some additional Python tricks to do that. No, .name merely changes the top level design name from its default. The name is also used to define a filename, but that cannot be further controlled at this point. I guess we should add an additional attribute (.filename ?) to control the desired filename. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a hardware description language: http://www.myhdl.org |