[myhdl-list] Another newbie question

[Newell J. <pil...@gm...>]

All,

Is there a way to delay signals when converting to Verilog?

I want to be able to convert using toVerilog to produce something like this:

a <= #1 b;

I have tried different approaches but the best I have figured out is doing
something like this:

if something:
   yield delay(1)
   a = b
...
...

which gets converted to:

#1
a <= b;

Any other suggestions?

Thanks,

-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits