[myhdl-list] Support for z and x signal levels in Verilog?

[Newell J. <pil...@gm...>]

I have searched the documentation and the wiki but was unable to find
anything in regards to whether or not MyHDL supports Verilog's high
impedance and undefined signal levels?

Does anyone know if there is a way to do this?

Thanks in advance,

-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits