Re: [myhdl-list] toVerilog conversion question

[Newell J. <pil...@gm...>]

>
>
> The last I heard, Guido doesn't like case/switch statements.  :-)


Thanks...but I am well aware of that.  Maybe you don't understand my
question.


>  If statements
> and concat() are what I would use.  The converter will insert case
> statements
> into the Verilog where appropriate.


Not necessarily.  I understand that if you have an enumeration or a tuple of
hardcoded values then it will work.  However, my question is whether or not
there is a way to update Signals with other Signals (i.e. Signals which
change on the right side of the non-blocking assignment <=).  I have been
having issues doing this and have not found anything in the documentation or
cookbook.

If you point me to a specific example then maybe I will see what you are
trying to say.  Thanks for the effort though.



>  I used the following LJ article to get
> going with this sort of thing:
>
> http://www.linuxjournal.com/article/7542
>
> The CookBook and other resources on myhdl.org are also very useful
> references.
>
> Cheers,
>
> - Brendan
>
>
>
> ------------------------------------------------------------------------------
> This SF.net email is sponsored by:
> SourcForge Community
> SourceForge wants to tell your story.
> http://p.sf.net/sfu/sf-spreadtheword
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits