Re: [myhdl-list] toVerilog conversion question

[Brendan R. <bre...@gm...>]

Newell Jensen <pillar2012 <at> gmail.com> writes:

> 
> All,I am trying to create a case statement in Verilog that relies on other
Signals such as this:(THIS WOULD BE THE VERILOG AFTER CONVERSION, where dwb_mx
is a Signal that is 32 bits)    4'h8: mem_mx <= #1 {24'd0, dwb_mx[31:24]};   
4'h4: mem_mx <= #1 {24'd0, dwb_mx[23:16]};    4'h2: mem_mx <= #1 {24'd0,
dwb_mx[15:8]};    4'h1: mem_mx <= #1 {24'd0, dwb_mx[7:0]};
>     . . .    . . .    . . .Is there a way to do this?  I have been struggling
to get my conversion to something like this and was wondering if it is
possible.  All the examples that I looked at online are case statements that
already know the values on the right side of => .  That is, when the tuple is
made with constants.  I guess I could do a bunch of if statements... but didn't
know if there was another way to do this more elegantly within MyHDL.Thanks,--
Newellhttp://www.gempillar.comBefore enlightenment: chop wood, carry waterAfter
enlightenment: code, build circuits

The last I heard, Guido doesn't like case/switch statements.  :-)  If statements
and concat() are what I would use.  The converter will insert case statements
into the Verilog where appropriate.  I used the following LJ article to get
going with this sort of thing:

http://www.linuxjournal.com/article/7542

The CookBook and other resources on myhdl.org are also very useful references.

Cheers,

- Brendan