[myhdl-list] toVerilog conversion question

[Newell J. <pil...@gm...>]

All,

I am trying to create a case statement in Verilog that relies on other
Signals such as this:
(THIS WOULD BE THE VERILOG AFTER CONVERSION, where dwb_mx is a Signal that
is 32 bits)

    4'h8: mem_mx <= #1 {24'd0, dwb_mx[31:24]};
    4'h4: mem_mx <= #1 {24'd0, dwb_mx[23:16]};
    4'h2: mem_mx <= #1 {24'd0, dwb_mx[15:8]};
    4'h1: mem_mx <= #1 {24'd0, dwb_mx[7:0]};
    . . .
    . . .
    . . .

Is there a way to do this?  I have been struggling to get my conversion to
something like this and was wondering if it is possible.  All the examples
that I looked at online are case statements that already know the values on
the right side of => .  That is, when the tuple is made with constants.  I
guess I could do a bunch of if statements... but didn't know if there was
another way to do this more elegantly within MyHDL.

Thanks,

-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits