[myhdl-list] Control over output file generation

[Eric J. <jo...@MI...>]

Hello! MyHDL has been a lot of fun thus far, but as I look toward
automating more of my design flow, I'm stuck on one question: The
correct way to control both the location and name of the generated
verilog/vhdl code. 

In particular, how do I tell toVerilog() to dump the output file
in /foo/bar/baz.v?  And is it at all possible to control the filenames
that the different contained modules will be generated as? I have some
code analysis and automated build tools that I'm trying to interoperate
with. 

Thanks again, 
		...Eric