Re: [myhdl-list] Conversion of Signal(intbv(False))

[Jan D. <ja...@ja...>]

Christopher L. Felton wrote:
> Is it expected behavior that a Signal(intbv(<bool>)) is not converted?
> 
> Error recieved:
> Jan_17_2009 cfelton$ python no_bool.py
> Traceback (most recent call last):
>   File "no_bool.py", line 32, in <module>
>     convert()
>   File "no_bool.py", line 28, in convert
>     toVerilog(no_bool,clk,rst,a,b,sel,c)
>   File "/Library/Python/2.5/site-packages/myhdl/conversion/ 
> _toVerilog.py", line 111, in __call__
>     siglist, memlist = _analyzeSigs(h.hierarchy)
>   File "/Library/Python/2.5/site-packages/myhdl/conversion/ 
> _analyze.py", line 95, in _analyzeSigs
>     raise ConversionError(_error.UndefinedBitWidth, s._name)
> myhdl.ConversionError: Signal has undefined bit width: a
> 
> 
> This can be worked around by adding bit width, Signal(intbv(False) 
> [1:]).  But if this is done the code (or at least the example below)  
> doesn't work, because the intbv type insn't a bool anymore.  Once the  
> bit width is added it becomes an integer and the conditions will fail  
> for a non-bool type.

What exactly doesn't work about that? Conversion seems to work fine,
and I don't immediately see what would be wrong with the Verilog or VHDL
code.

Also, before going into the depth of the matter, what's against
simply using Signal(False) for the boolean signals?



> 
> 
> from myhdl import *
> 
> def no_bool(clk, rst, a, b, sel, c):
>     """
>     Boolean intbv not supported?
>     """
>     @always(clk.posedge or rst.posedge)
>     def rtl():
>         if sel:
>             c.next = b
>         else:
>             c.next = a
> 
>     return rtl
> 
> def convert():
>     clk = Signal(intbv(False))
>     rst = Signal(intbv(False))
>     a   = Signal(intbv(False))
>     b   = Signal(intbv(False))
>     sel = Signal(intbv(False))
>     c   = Signal(intbv(False))
> 
>     toVerilog(no_bool,clk,rst,a,b,sel,c)
>     toVHDL(no_bool,clk,rst,a,b,sel,c)
> 
> if __name__ == '__main__':
>     convert()
> 
> 
> 
> Thanks
> 
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
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