Re: [myhdl-list] code generation compatibility with old Verilog/VHDL

[Jan D. <ja...@ja...>]

Andrew Stone wrote:
> Thanks, for your reply, Jan!
> 
> I think that there may be a bug in the intbv bounds checking logic.
> Maybe because Python is a little too clever when you do two's
> complement by hand?
>>>> print (~5)+1
> -5
> 
> So I can't really do two's complement by hand to create negative
> numbers... see inline for more details. 

That may be right. Bit inversion on constrained intbv's works
differently though - if min>0, it will return positive numbers.
But even then, thinking about it, it may be much more complicated
than in Verilog to emulate signed behavior with only "unsigned"
intbv's. MyHDL strictly checks bounds, Verilog typically just
does operations compatible with 2's complement arithmetic, even
with only positive numbers.

 > also, I've included a couple
> of the syntax errors that I'm getting in the verilog and vhdl
> compilation.  But I'd like to emphasize that if the problems are
> caused by the fact that my synthesis tool is old (2002) then pls don't
> fix just on my account! :-)  Instead let's think about whether
> compatibility with old systems is a priority for myHdl.  It may very
> well be.  For example Linux has a pretty thriving community of people
> putting it on old junker computers...

Very old and limited tools indeed seem to be the culprit, see further.
I would hesitiate very much to include this in the main MyHDL code
(why support abondoned tools?). However, it seems easy to fix your
issues locally by a few patches. (You could do this in a local
mercurial clone that still tracks future development.)


> Specific responses below:
> 
> Thanks for your help,
> Andrew



> The synthesis tool does not like the comma in @(reset,clk).  But it
> works if I use "or":

Verilog-2001.


>> There's no escape: you have to understand what Verilog/VHDL your
>> synthesis tool understands.
> 
> I hope this will not always be true -- for example most C programmers
> would be hard pressed to understand the generated assembly code.

Note that I wasn't talking about the synthesis tool output - that's
another subject. I was talking about the *input*.

I'm pretty sure it will stay like that for the following reason. It
would actually be pretty simple to design a HDL that could be
synthesized "completely". There have in fact be many attempts.
In fact people are still trying.

But all attempts have failed, and that should tell us something.
It tells us that such languages are too simple for serious
modelling and test benches. The kind of HDL that people want
is one that is very powerful for modeling/simulation in the first
place. Synthesis is just one thing that people want to do
with some of the models, and it naturally much more limited.
Note that software doesn't have this simulation / synthesis duality.

There is a reason why Verilog and VHDL are winners instead of the
myriad of implementation-centric attempts. MyHDL is happy to be
in the same camp.

> 
> One other issue was that in the generated code pck_myhdl_06dev10 there's a line:
> 
> attribute enum_encoding: string;
> 
> This line causes the error:
> pck_myhdl_06dev10.vhd (line 11, col 29):  (E56) Expected OF, but got :

Standard VHDL ...
This is only needed if you use enum types in MyHDL source code.

> 
> Next, my generated code looks like this:
> 
> -- File: bresStepTest.vhd
> -- Generated by MyHDL 0.6dev10
> -- Date: Mon Dec 22 22:50:13 2008
> 
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.numeric_std.all;
> --use std.textio.all;
> 
> use work.pck_myhdl_06dev10.all;
> 
> entity bresStepTest is
>     port (
>         clk: in std_logic;
>         reset: in std_logic;
>         osc: in std_logic;
>         oscCount: inout unsigned(31 downto 0);
>         coils: inout unsigned(3 downto 0);
>         stepType: in std_logic
>     );
> end entity bresStepTest;
> 
> architecture MyHDL of bresStepTest is
> 
> signal nextPos: signed (31 downto 0);
> signal nextTime: signed (31 downto 0);
> signal loaded: std_logic;
> signal testTime: signed (31 downto 0);
> signal bresCircuit_timeLeft: signed (31 downto 0);
> signal bresCircuit_deltaTime: signed (31 downto 0);
> signal bresCircuit_deltaPos: signed (31 downto 0);
> signal bresCircuit_cPos: signed (31 downto 0);
> signal bresCircuit_curCtr: signed (31 downto 0);
> 
> begin
> 
> 
> BRESSTEPTEST_DRIVEMOTORCMDS: process (clk) is
> begin
> 
> And I get an error:
> main.vhd (line 38, col 46):  (E10) Syntax error at/before reserved symbol 'is'.


Consistent support for "is" keyword was introduced in VHDL-93.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a hardware description language:
     http://www.myhdl.org