Re: [myhdl-list] [new] design flow question

[Jan D. <ja...@ja...>]

Newell Jensen wrote:

>     I recently used this technique to write a simple high-level
>     behavioral model for a memory structure with a very complicated
>     Verilog model.
> 
> Yeah, unfortunately I am not as keen on myhdl as you are (I mean, you 
> wrote it and all).  If I could do this for the CPU, bus, UART, and the 
> Verilog Wishbone wrapper that I need to make for my DDR2 SDRAM (Xilinx 
> Core Generator generated) I would be set.
> 
> However, I don't see that happening unless I knew what to do etc. and 
> unfortunately I don't.

At least I saved you some frustration up-front :-) No matter how keen I
may be on myhdl, it's more important to be honest and avoid frustration.
Using MyHDL without simulation will get you into trouble. To simulate,
you need models. At this point, MyHDL doesn't have a library like
opencores. It's that simple.

I suggest you use Verilog to tie things together and simulate at the
top level.

If you still want to experiment with MyHDL, do it bottom-up for some
module that you may have design and verify separately. After conversion,
you can then include into the Verilog top-level.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
     http://www.myhdl.org