Re: [myhdl-list] [new] design flow question

[Newell J. <pil...@gm...>]

On Tue, Dec 23, 2008 at 2:53 AM, Jan Decaluwe <ja...@ja...> wrote:

> Newell Jensen wrote:
> > I wanted to ask some questions that are similar to the ones that Neal
> > asked.  I am new to HDL design in general but love programming in
> > Python.  However, I think I will be using a bunch of the open source
> > cores that are on OpenCores.org.
> >
> > I would love to start using MyHDL on a regular basis but as of now I
> > don't really see how I can use MyHDL with all the OpenCores that I would
> > be using (I am new so if the answer is obvious than excuse me for my
> > ignorance...I am still learning).
> > It would really be nice if there was a way to wrap these cores for use
> > in MyHDL so that in the end I could have a Top Level MyHDL
> > implementation with embedded cores from OpenCores.
> >
> > Any ideas if this is possible?
>
> The trick is to include an instantiation of the core using user-defined
> code hooks. As Gunter suggests, you should find sufficient documentation
> on this.
>
> I'd just like to add a methodology note. It is always desirable to do
> simulation, not just using MyHDL as a convertor. Simulation will find
> problems that the convertor won't (and can't).
>
> Unfortunately, this means you still need a MyHDL model for such a core.
> However, note that when you use a user-defined code hook, the convertor
> stops converting at that point. So you can write a model at the highest
> level possible using all tricks in the Python book without being
> concerned about convertibility.
>

Some of the cores that I am using from OpenCores.org are a CPU....which I
would have no idea on how to do this.  I wish I did, but I am still new to
all this for the most part.


>
> I recently used this technique to write a simple high-level
> behavioral model for a memory structure with a very complicated
> Verilog model.


Yeah, unfortunately I am not as keen on myhdl as you are (I mean, you wrote
it and all).  If I could do this for the CPU, bus, UART, and the Verilog
Wishbone wrapper that I need to make for my DDR2 SDRAM (Xilinx Core
Generator generated) I would be set.

However, I don't see that happening unless I knew what to do etc. and
unfortunately I don't.

Thanks for all the suggestions to everyone though.


>
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      From Python to silicon:
>     http://www.myhdl.org
>
>
>
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-- 
Newell

http://www.gempillar.com
Before enlightenment: chop wood, carry water
After enlightenment: code, build circuits