Re: [myhdl-list] code generation compatibility with old Verilog/VHDL

[Jan D. <ja...@ja...>]

G.A...@gm... wrote:
> Hi myHdlers,
> 
> I'm using an old cypress CPLD: CY37000 chip and so I'm using an old 
> synthesis tool: Warp 6.3 (2002). I'm seeing some compile errors in both 
> the generated Verilog and VHDL code and I'm assuming that they have to 
> do with using a very old synthesis tool.

Probably, but not necessarily. MyHDL can convert much more than can
reasonably be synthesized. For better info, you'd have to tell us
more about the kind of compile errors you get.

There's no escape: you have to understand what Verilog/VHDL your
synthesis tool understands.

With MyHDL, there's an additional complication: you have to understand
how get supported HDL code out of the convertor. With a little practice,
this shouldn't be hard, as there is a pretty close mapping from
the MyHDL input to the HDL output.

> In the Verilog code, I was able to make small changes to get my design 
> to synthesize, until I hit a problem that Warp 6.3 does not support 
> signed regs... *sigh*. I'm guessing this is rare enough that no one is 
> interested in putting automatic generation of signed logic in the 
> myHdl->Verilog generator?

Indeed. Your option here is to do what Verilog designers had to do for a
very long time (until the language had signed): emulate signed behavior
manually using unsigneds only.

> So I noticed that Warp 6.3 does support signed logic in VHDL, so Great! 
> I can use the cool new 0.6 feature! Well...no. There are errors in the 
> VHDL synthesis also, and I don't know VHDL at all...
> 
> Is there any interest in supporting old versions? Some of the problems 
> seem to be simple syntax changes, or optional libraries (for example, in 
> vhdl "use std.textio.all" (no textio library found).

std.textio is actually only required for printing. I guess I could
make the convertor more intelligent by only including it when needed.
On the other hand, it's a standard package that any VHDL tool should
know about.

> BTW, As a quick "fix" it might be nice to put the language version in 
> the comment so that people know what the generated code is targeted to.

I guess you mean the Verilog or VHDL version? At this moment this is
just based on an estimated conservative common ground.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
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