[myhdl-list] code generation compatibility with old Verilog/VHDL

[<G.A...@gm...>]

Hi myHdlers,

I'm using an old cypress CPLD: CY37000 chip and so I'm using an old  
synthesis tool: Warp 6.3 (2002). I'm seeing some compile errors in both the  
generated Verilog and VHDL code and I'm assuming that they have to do with  
using a very old synthesis tool.

In the Verilog code, I was able to make small changes to get my design to  
synthesize, until I hit a problem that Warp 6.3 does not support signed  
regs... *sigh*. I'm guessing this is rare enough that no one is interested  
in putting automatic generation of signed logic in the myHdl->Verilog  
generator?

So I noticed that Warp 6.3 does support signed logic in VHDL, so Great! I  
can use the cool new 0.6 feature! Well...no. There are errors in the VHDL  
synthesis also, and I don't know VHDL at all...

Is there any interest in supporting old versions? Some of the problems seem  
to be simple syntax changes, or optional libraries (for example, in  
vhdl "use std.textio.all" (no textio library found).

BTW, As a quick "fix" it might be nice to put the language version in the  
comment so that people know what the generated code is targeted to.

Finally, just as a shot in the dark, does anyone know of a more modern free  
synthesis tool that can target CY37256P160-83AC?

Regards,
Andrew