Re: [myhdl-list] [new] design flow question

[Jan D. <ja...@ja...>]

Neal Becker wrote:
>
>>
> I'm still a bit lost.  My question is, suppose, for example,  I want to do a design targetting Xylinx.  Suppose I want to use an FIR filter, using Xylinx FIR core generator.  
> Would this work with a myhdl frontend, and if so, how would the design flow go?

MyHDL is "front-end" in a HDL-based design flow, as an alternative
to Verilog or VHDL. In the ideal case, your HDL designs are
technology-independent, which means that they contain no references
to primitives of specific target technologies. Targetting to
a specific technology is decoupled from this and is accomplished
by a synthesis tool.

The big advantage of HDL-based design like that, is that you are
not tied to a specific vendor, technology or device.

This ideal can be approached very closely, but for obvious
reasons it's not necessarily in an FPGA vendors interest
to tell you this or promote it. Consequently, one obverves
a great deal of difference in "technology independence"
between various design teams. If you want it, you have to
plan for it and keep the discipline.

I have never used any Xilinx core generator, but I assume
that its output is in terms of Xilinx primitives. If so,
this is not compatible with true HDL-based design as outlined
above.

An HDL-based solution could be as follows. Write a fully
parametrized core generator e.g. for a FIR filter in
MyHDL. (It's ideal for such work, seems easy.) Generate
your coefficients using a filter design package, fill
them in, resimulate in MyHDL, convert to Verilog/VHDL.

The output would be technology independent Verilog or
VHDL code for that filter, that you can then target
to anything using a synthesis tool: Xilinx, Altera,
Actel, ASIC implementation ...

Jan

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