Re: [myhdl-list] [new] design flow question

[Jan D. <ja...@ja...>]

Neal Becker wrote:
> I know only a little about Verilog - I do algorithm development and hand off to coworkers who produce verilog.
> 
> We typically do a lot of DSP work (lots of arithmetic).  Often, things like Xylinx cores are used.
> 
> Would that sort of design flow work with a myhdl frontend?  Any hints?

Sure. This seems to be exactly the case recently highlighted by Chris,
and just added to the advocacy page:

http://www.myhdl.org/doku.php/why#you_would_like_to_do_algorithm_development_and_implementation_in_the_same_environment

Jan

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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Using Python as a hardware description language:
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