Re: [myhdl-list] [new] design flow question

[Felton C. <chr...@gm...>]

On the website there are many examples, check out some of the  
following links.

http://www.myhdl.org/doku.php/publications  -- This is your one stop  
shop, the paper by Dillon Engineering (a bunch of active MyHDL  
contributors) describes exactly what you are looking for (http://www.myhdl.org/doku.php/publications 
).

Different examples that have been contributed to the site
http://www.myhdl.org/doku.php/cookbook:sinecomp   -- Implementation of  
the cordic
http://www.myhdl.org/doku.php/cookbook:bitonic   	-- Sort algorithm  
implementation
http://www.myhdl.org/doku.php/projects:cordic_calculations	-- Another  
cordic
http://www.myhdl.org/doku.php/projects:gcicexample	-- CIC Filter
http://www.myhdl.org/doku.php/projects:conste_encoder  --  
Constellation Encoder

Good luck


On Dec 17, 2008, at 7:34 PM, Neal Becker wrote:

> I know only a little about Verilog - I do algorithm development and  
> hand off to coworkers who produce verilog.
>
> We typically do a lot of DSP work (lots of arithmetic).  Often,  
> things like Xylinx cores are used.
>
> Would that sort of design flow work with a myhdl frontend?  Any hints?
>
>
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