[myhdl-list] [new] design flow question

[Neal B. <ndb...@gm...>]

I know only a little about Verilog - I do algorithm development and hand off to coworkers who produce verilog.

We typically do a lot of DSP work (lots of arithmetic).  Often, things like Xylinx cores are used.

Would that sort of design flow work with a myhdl frontend?  Any hints?