Re: [myhdl-list] IEEE STANDARDIZATION

[Christopher L. F. <cf...@uc...>]

> When will the final release for 0.6 be ready.  In the past, I have  
> been having some issues with Mercurial.  I have been working them  
> out.  However, I may need help.  Is anyone out there willing to help?
>
> And Lastly,..............
>
> I was wondering if MyHDL can or EVER will be submitted directly to  
> the institute of Electronics and Electrical Engineers ( IEEE ) for  
> obtaining UNIVERSAL and International standardization?  Where MyHDL  
> no longer has to be converted directly to either VHDL or Verilog?  I  
> STRONGLY believe that having to finally convert MyHDL source to  
> Verilog or VHDL constrains the unique advantages of utilizing MyHDL  
> within the Python programming language framework for hardware  
> development for both FPGAs and ASICS.
>
> As an End Game Approach, the idea that I am trying to transmit is  
> that we as a collective could write a proposal to the IEEE, where  
> they will then develop a standardization for the MyHDL language.   
> The same type of standardization that has been bestowed to both  
> Verilog and VHDL.  This would allow companies like XILINX, ALTERA,  
> IBM, INTEL, Cadence to confident enough to develop synthesizers for  
> MyHDL, where there would no longer be a critical need to convert  
> MyHDL to either Verilog to VHDL.  Where a design that is not be  
> synthesized onto an ASIC or FPGA, could be become so with this  
> approach...
>
> I believe that the National Institute of Standards and Technology  
> (NIST) might be more than happy to bring about international  
> standardization for MyHDL.  There is a strong need within the  
> scientific communities to develop reconfigurable computing for  
> numerical methods.
>
> I believe that in the end that giving MyHDL the following possible  
> designations,
>


Hmmm, there is nothing stopping anyone from creating a MyHDL to gate- 
level netlist directly.  I think what Jan has done is brilliant.  He  
leveraged existing technology and tools without having to recreate a  
lot of work.  This has allowed him and others to focus on MyHDL and  
not the back end conversion.  I also think this is the correct approach.

I don't think standards are bad (not too much experience here) but I  
do think there would be a disconnect between development and the  
standardization.  Probably look at other languages for present and  
past experiences.

I think MyHDL will grow with more adoption, this requires more  
individual developers using MyHDL in their design flows and more  
success stories.

Because MyHDL outputs Verilog/VHDL it is minimal risk to add MyHDL to  
the design flow.  Personally, I like the current model.  It would be  
great to see many more developers involved and the project grow as it  
is.  As Jan has pointed out MyHDL is fully functional.  It is up to us  
developers to create some interesting works utilizing MyHDL and Python  
(I am personally working on a time reclamation tool :)

At this point there is a focal point and no competing "standards".  I  
think Jan overseeing/controlling MyHDL as the project he created is  
good.  He is very open to others comments and input.  Because of this  
MyHDL has been maturing.  There are no different/competing versions  
because company A did something different than company B.  Companies  
may become interested in MyHDL because it helps promote their tools  
(if they are good tools).


> ANSI MyHDL or ISO MyHDL, might be a benefit for the entire hadware  
> development community.
>
> So,
>
> What does everybody think about this plan.  I would love to have  
> this plan apart of my thesis endeavor at Wright State University.

As previously mentioned, I think what would help this project the most  
is more success stories and adoption.  Example for you studies if you  
were able to create a working ASIC using the MyHDL flow that would be  
very impressive (mosis education program).   You are in luck that you  
have a group of experienced developers that would help guide you in  
the usage of MyHDL.

Thanks

On Dec 17, 2008, at 6:47 AM, David Blubaugh wrote:

>
>
> Thanks to All,
>
> David Blubaugh
>
>
>
>
>
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