[myhdl-list] IEEE STANDARDIZATION

[David B. <dav...@ya...>]

When will the final release for 0.6 be ready.  In the past, I have been having some issues with Mercurial.  I have been working them out.  However, I may need help.  Is anyone out there willing to help?
 
And Lastly,..............
 
I was wondering if MyHDL can or EVER will be submitted directly to the institute of Electronics and Electrical Engineers ( IEEE ) for obtaining UNIVERSAL and International standardization?  Where MyHDL no longer has to be converted directly to either VHDL or Verilog?  I STRONGLY believe that having to finally convert MyHDL source to Verilog or VHDL constrains the unique advantages of utilizing MyHDL within the Python programming language framework for hardware development for both FPGAs and ASICS.  
 
As an End Game Approach, the idea that I am trying to transmit is that we as a collective could write a proposal to the IEEE, where they will then develop a standardization for the MyHDL language.  The same type of standardization that has been bestowed to both Verilog and VHDL.  This would allow companies like XILINX, ALTERA, IBM, INTEL, Cadence to confident enough to develop synthesizers for MyHDL, where there would no longer be a critical need to convert MyHDL to either Verilog to VHDL.  Where a design that is not be synthesized onto an ASIC or FPGA, could be become so with this approach...
 
I believe that the National Institute of Standards and Technology (NIST) might be more than happy to bring about international standardization for MyHDL.  There is a strong need within the scientific communities to develop reconfigurable computing for numerical methods.  
 
I believe that in the end that giving MyHDL the following possible designations,
 
ANSI MyHDL or ISO MyHDL, might be a benefit for the entire hadware development community.  
 
So,
 
What does everybody think about this plan.  I would love to have this plan apart of my thesis endeavor at Wright State University.  
 
 
Thanks to All,
 
David Blubaugh