Re: [myhdl-list] Dynamically Generated Assignments

[Evan B. <br...@mi...>]

Jan Decaluwe wrote:
> Evan Broder wrote:
>> Hi -
>>     I'm trying to write a (HDL) module to permute an input bit-vector
>> from a mapping list that's fed in when the module is initialized, but I
>> can't seem to get it to work. I've gone through a bunch of different
>> revisions trying to make this work, and finally settled on trying to
>> generate one generator for each assignment so that I could loop without
>> MyHDL trying to convert the loop to Verilog. I think that code will
>> explain this much better than I can, so:
>>
>> def module(self, clock, in_perm, out_perm):
>> 	permutations = []
>> 	for i in range(len(mapping)):
>> 		input_index = mapping[i]
>> 		@always_comb
>> 		def permute():
>> 			out_perm.next[i] = in_perm.val[input_index]
>> 		
>> 		permutations.append(permute)
>> 	
>> 	return tuple(permutations)
>>
>> For some reason, though, it seems that each generator overwrites the old
>> one, meaning that only the last bit of out_perm ever gets set.
>
> This is a consequence from how "free variables" (i) are handled in Python.
> Consider:
>
> def f():
>      funcs = []
>      i = 0
>      def g():
>          print "func 1"
>          print i
>      funcs.append(g)
>      i = 1
>      def g():
>          print "func 2"
>          print i
>      funcs.append(g)
>
>      for h in funcs:
>          h()
>
> f()
>
> The output is:
>
>  > python tmp4.py
> func 1
> 1
> func 2
> 1
>
> So, the functions are different, but the value of the free variable
> is the "last" one in both cases.
>
>> Is there some way that I can make this work the way that I want?
>
> It would be quite easy to accomplish what you want with
> lists for Signals instead of bit vectors modeled by intbv's.
> Would that be acceptable?
>
> Jan
>

I don't want the interface to the module to change (I want the inputs
and outputs to be bit vectors). Are you suggesting that I should change
the arguments or convert the intbv's to lists within the module/function?