[myhdl-list] Dynamically Generated Assignments

[Evan B. <br...@mi...>]

Hi -
    I'm trying to write a (HDL) module to permute an input bit-vector
from a mapping list that's fed in when the module is initialized, but I
can't seem to get it to work. I've gone through a bunch of different
revisions trying to make this work, and finally settled on trying to
generate one generator for each assignment so that I could loop without
MyHDL trying to convert the loop to Verilog. I think that code will
explain this much better than I can, so:

def module(self, clock, in_perm, out_perm):
	permutations = []
	for i in range(len(mapping)):
		input_index = mapping[i]
		@always_comb
		def permute():
			out_perm.next[i] = in_perm.val[input_index]
		
		permutations.append(permute)
	
	return tuple(permutations)

For some reason, though, it seems that each generator overwrites the old
one, meaning that only the last bit of out_perm ever gets set.

Is there some way that I can make this work the way that I want?

Thanks,
   Evan