Re: [myhdl-list] Tristate bus to external SRAM
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From: Jan D. <ja...@ja...> - 2007-12-16 23:05:05
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Randy Lea wrote:
> Thanks for all the work on MyHDL.
Thanks for the interest.
> The project I'm looking at requires Tri-state signals for external 8-bit data
> path to memory. I noticed that the latest dev release (0.6dev4) includes
> Tri-state support for simulation. I have installed dev4, all of the examples
> run, but I am having difficulty using the Tri-state signals. I have a lot of
> experience in Python, none with MyHDL.
>
> Is the dev4 release stable enough to use for simulation?
In general, for all features in earlier releases (1.5.1) it should be stable or
better because of bug fixes. Features under development will be buggy
or incomplete.
> Is the Tri-state signal working?
There is in an experimental implementation (corresponding to MEP 103)
in 0.6dev4. No extensive testing or unit tests yet though.
> If yes, could you post a simple example of using a Tri-state signal?
Sure. Here is the example that I used to quickly check the experimental
implementation. Let me know if this functionality is what you're looking
for:
---
from myhdl import *
def test(bus):
d1 = bus.driver()
d2 = bus.driver()
d3 = bus.driver()
@instance
def proc1():
for v in (1, None, 2, None, 3, 10, None, None):
yield delay(10)
d1.next = v
raise StopSimulation
@instance
def proc2():
for v in (None, 4, None, 5, 6, None, None):
yield delay(10)
d2.next = v
@instance
def proc3():
for v in (None, None, None, None, None, None, 44):
yield delay(10)
d3.next = v
@always(bus)
def monitor():
print now(), bus
return proc1, proc2, proc3, monitor
bus = Tristate(intbv(0)[4:])
sim = Simulation(test(bus))
sim.run()
---
Output:
> python test.py
10 1
20 4
30 2
40 5
** BusContentionWarning: Bus contention
** BusContentionWarning: Bus contention
** BusContentionWarning: Bus contention
50 None
60 10
70 44
---
Regards,
Jan
--
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Kaboutermansstraat 97, B-3000 Leuven, Belgium
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