Re: [myhdl-list] Tristate bus to external SRAM

[Randy L. <Dog...@bl...>]

George Pantazopoulos <george <at> gammaburst.net> writes:

> 
> 
> On Wed, December 13, 2006 9:16 am, Jan Decaluwe wrote:
> > George Pantazopoulos wrote:
> >>>At some point I would like to take some time to think thorougly
> >>>about tristates and inouts and come up with a satisfactory
> >>>solution, hopefully based on user inputs and feedback.
> >>>Currently, I'm focussed on getting toVHDL on track
> >>>and right - which offers more than enough brain teasers 



Thanks for all the work on MyHDL.

The project I'm looking at requires Tri-state signals for external 8-bit data
path to memory. I noticed that the latest dev release (0.6dev4) includes
Tri-state support for simulation. I have installed dev4, all of the examples
run, but I am having difficulty using the Tri-state signals. I have a lot of
experience in Python, none with MyHDL.

Is the dev4 release stable enough to use for simulation?

Is the Tri-state signal working?

If yes, could you post a simple example of using a Tri-state signal?

Thanks again.