Re: [myhdl-list] classes as interfaces

[Tom D. <TD...@di...>]

I agree this that having something along this line would be useful.

Some time ago, I tried to create a class that would represent a complex 
number, basically a real and imaginary signal that I could just pass around 
as a single signal. 

It worked fine, till I tried to use toVerilog, then ran into troubles that I 
couldn't get around. 

toVerilog would need to accept an object of a class as I/O and look inside the 
object for any signals, each one of them becoming a port. 

I'm sure that is way over simplified, but that is the idea.

Tom


On Tuesday 09 October 2007 09:48:00 pm Patricio Kaplan wrote:
> Hello, let me start by saying that I think myHDL is really cool. I am
> playing with it and I see lots of potential.
>
> I am trying to use a class as a system verilog interface, i.e. as a
> collection of signals. It does not seem to synthesize though. I saw a
> previous posting related to this, but I just want to present an example
> where classes come handy.
>
> Can anyone tell me if this is illegal and if so, what is the right
> approach?
>
> thanks!
> -patricio
>
>
> class spi_if:
>         # class attributes
>         srdy = Signal(intbv(0)[1:0])
>         drdy = Signal(intbv(0)[1:0])
>         size = Signal(intbv(0)[3:0])
>         data = Signal(intbv(0)[64:0])
>         sop  = Signal(intbv(0)[1:0])
>         eop  = Signal(intbv(0)[1:0])
>
> def padder(padding, count, rx_spi, tx_spi, clk, rst):
>
>     @always_comb
>     def comb():
>         rx_spi.drdy.next=(int(tx_spi.drdy==1 and padding==0 or
> tx_spi.srdy==0))
>
>     @always(clk.posedge)
>     def seq():
>         if rst:
>                 padding.next=0
>                 count.next=0
>                 tx_spi.srdy.next=0
>         elif tx_spi.srdy==0 or tx_spi.drdy==1: # ready for new flit
>                 if padding:
>                         tx_spi.srdy.next=1
>                         count.next= count+8
>                         if (count+8)==64:
>                                 padding.next=0
>                 elif rx_spi.srdy==1:
>                         tx_spi.srdy.next=1
>
>                         if rx_spi.eop==1 and rx_spi.size!=0:
>                                 tmp_count = count + rx_spi.size.val
>                         else:
>                                 tmp_count= count + 8