[myhdl-list] FW: MyHDL help
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From: Narasimhan, S. \(Sarath\) <sa...@al...> - 2007-10-06 19:04:27
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Jan
I am having problems when passing lists of signals to functions
decorated by @always_comb
See below
Sarath
-----Origin al Message-----
From: Narasimhan, Sarath (Sarath)=20
Sent: Friday, October 05, 2007 6:57 PM
To: Narasimhan, Sarath (Sarath); 'ja...@ja...'
Subject: RE: MyHDL help
Jan
Attached are sample files that show that list(s) don't appear to work
properly for example simple_int_list.py and simple.py have lists and
the print function within the combinatorial process only enters once
versus simple_int.py which enters everytime the counter changes value.
Does your decorators support lists of signals within parameters of
functions.
Is there a potential work around
Sarath
=20
-----Original Message-----
From: Narasimhan, Sarath (Sarath)
Sent: Friday, October 05, 2007 2:41 PM
To: 'ja...@ja...'
Subject: RE: MyHDL help
Jan
I have the following code. The generator enters only once even though I
see calling function Change the value of list of signals test almost
every clock Though Test_func runs only once even though test value
changes What am I doing wrong. Does @always_comb support arbitrary list
of signals
test=3D[Signal(intbv(0)) for i in range(n)]
ntest=3D[Signal(intbv(0)) for i in range(n)]
def Test_func(ntest,test):=20
@always_comb() // enters only once with initial value
doesn't enter as test changes
def tl():
print test =20
ntest=3Dtest
return tl
def sync_funct
@posedge.clk
def sl():
print test // prints actual varying value of test
return sl
Ti =3D Test_func(ntest,test)
si =3D sync_funct
return Ti, si
-----Original Message-----
From: Jan Decaluwe [mailto:ja...@ja...]
Sent: Tuesday, June 12, 2007 2:29 AM
To: Narasimhan, Sarath (Sarath)
Subject: Re: MyHDL help
Narasimhan, Sarath (Sarath) wrote:
> A question: Does Myhdl have any utilities to convert from Verilog to=20
> Python
No. That would be a very tough project.
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