Re: [myhdl-list] functional verification

[Tom D. <TD...@di...>]

Jan,

I have to respond to both points, almost missed your comments:

> I have nothing against love (I became a father again recently
> which partially explains my MyHDL "inactivity") and in fact I
> believe any undertaking should have its dose of it, but if
> it stays to that in this project, I will consider it a failure :-)

Congratulations! My youngest of 4 is now 1 1/2 years. Which means I have not 
had as much time as I would like to advance our use of MyHDL in our normal 
project flows. Getting there now though.

BTW, I also have a 5th child for this school year, a 18 year old exchange 
student from Belgium. She if from a little town near Chimay, not sure how 
close that is to you...
 
>
> I am explicitly looking for industrial relevance. Actually
> I know that several corporations are using MyHDL, also large ones,
> though so far only one has "outed" itself to my knowledge
> (Dillon engineering). I hope others follow their example!

Speaking of "outing", last week I gave a presentation at HPEC 2007 based on 
how we use Python to accelerate our FPGA/ASIC development. Of course 
mentioned MyHDL and got the chance to explain our use of it. Also pointed 
quite a few to the MyHDL web site.

I will post the presentation and send a link to this list in the next few 
days.

Tom