Re: [myhdl-list] functional verification

[Jacob R. <jac...@gm...>]

I come from an RF / analog background so I typically don't write
verilog that will be synthesized. I have started writing verilog
models of our RF and analog blocks to help the digital guys verify
connections to our blocks. The hard part there is the functional
verification. Since I want lots of flexibilty, MyHDL looked very
promising as a HVL. It seems to me if you are a small digital company
and can't afford tools like SpecMan, it is a good choice.

jr

On 9/26/07, Jan Decaluwe <ja...@ja...> wrote:
> Jacob Rael wrote:
> > Jan,
> >
> > Thanks for your quick reply. I understand that open source projects
> > tend to be a labor of love.
>
> I have nothing against love (I became a father again recently
> which partially explains my MyHDL "inactivity") and in fact I
> believe any undertaking should have its dose of it, but if
> it stays to that in this project, I will consider it a failure :-)
>
> I am explicitly looking for industrial relevance. Actually
> I know that several corporations are using MyHDL, also large ones,
> though so far only one has "outed" itself to my knowledge
> (Dillon engineering). I hope others follow their example!
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Kaboutermansstraat 97, B-3000 Leuven, Belgium
>      From Python to silicon:
>      http://myhdl.jandecaluwe.com
>
>
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-- 
Jacob Rael
jac...@gm...