[myhdl-list] functional verification
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From: Jacob R. <jac...@gm...> - 2007-09-24 23:15:20
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Hello all, I ran across myhdl when I first started learning Python and it looked really interesting. I am currently looking at how to do functional verification on our designs. We are a mixed signal group and we deal with analog signals at ports. Many of the HVL tools available assume only digital signals so I am expanding my search beyond specman. I like myhdl because it is Python based and I can see an easy path from design verification based on simulation to chip verification based on lab tests all within the same Python environment. I started looking at the Ruby tool, Ruby-vpi. On the surface, it looks like it can do everything I want to do but I have not dived down into the details. Also, I don't want to learn a new language. So, I have a few questions: 1. Our main simulator is ncsim. From the little I have read, I would have to write a C-program to allow myhdl to talk via PLI to ncsim. Has this already been written? What about other commercial simulators? 2. Is there any limitation in myhdl (or PLI) that would prevent analog (wreal or electrical) signals from traveling in and out of ports? 3. Has anyone built a complete verification environment in myhdl? 4. How active is the development on myhdl? The main Google links give the impression there isn't much going on. I didn't discover the posts on the newsgroups or the new site until I started digging deeper. I am glad I saw recent posts. At first I thought the project had been stagnant since version 0.5.1. jr -- Jacob Rael jac...@gm... |