Re: [myhdl-list] intbv.saturate, intbv.wrap

[Thomas T. <tho...@de...>]

I agree with Tom. There is not much use of wrap around in a DSP 
application. The only thing I know and where I first encountered this 
problem is a NCO. I tried it in the old fashioned way in myhdl.
For this single problem it is not worth to invest a lot of work in 
modifing _intbv. As I already told, I just considered wrap around as 
normal behaviour. (Jan might be right, when he states, that not applying 
_checkBounds will make myhdl behave like a python int, but the verilog 
code would wap around.)

Jan wrote:
> Let's try to clarify this. What is your goal - modeling, or also
> conversion, synthesis and implementation?

My goal is to use myhdl for doing DSP on an FPGA chip. I want to use 
MyHDL instead of Simulink. I just started to work with QuartusII on a 
Altera Cylcone chip.
Of course, I not only want to programm the FPGA via myHDL, I also want 
to do extensive testing and simulation with myHDL.

> If it's also conversion and implementation, I think you'll have to lower
> your expectations drastically. There are a lot of severe restrictions,
> similar to restrictions on synthesizable HDL code.

Yes, I am currently in the phase of discovering these restrictions and 
unfortunately having some difficulties to distinguish between bug and 
restriction.

> Again, I don't know if DSP languages such as Simulink do this (conversion
> and implementation), and if they do, it doesn't seem trivial (in general,
> for the whole set of operations).

For my current work tasks I can live without that features.
But, of course, it would be great, if myHDL evolves into a real 
alternative for Simulink.

Thomas