Re: [myhdl-list] toVHDL

[Jan D. <ja...@ja...>]

Thomas Heller wrote:
> Just because I'm curious:  *Why* do we need toVHDL?

Good question (and a great story btw).

I have commented on this briefly here:
    http://myhdl.jandecaluwe.com/doku.php/dev:whatsnew:0.6#rationale
but I'll elaborate on my current views further.

We certainly don't need toVHDL to close the gap to implementation.
As you note, since we have toVerilog, that is a done deal and
proven by now I believe. I have responded in this sense to some
initial requests for toVHDL, pointing out that there was no
real "urgency" anymore.

In fact, since we have toVerilog I believe MyHDL is more-or-less
a "complete" system that covers most aspects of modern hardware design.
So then the question becomes how to get more users, not features.
I remember a talk by Guido Van Rossum where he pointed out
that "once people use Python, we know that they will like it.
The problem is getting them to use it the first time".
I like to believe that it's the same for MyHDL.

So the problem then becomes to "lower the threshold". I see toVHDL
in that context, but again not as the most urgent effort. In fact,
the first thing I did for this was start up a Cookbook with real design
examples.

toVHDL is intended to lower the threshold for VHDL designers. It's
natural that designers want new things to fit in their current flow.
With toVHDL, they should be able to start using MyHDL and still
be fully compatible with their current VHDL-based design flow.

I have the impression that that holds for your case too. If toVHDL
would have been released already, perhaps you would have tried MyHDL
sooner (and you might also have realized sooner that you actually
don't need VHDL anymore :-))

With toVHDL, I believe we have two arguments to convince VHDL
designers. One is of course, Python itself - no need to elaborate
on that further here. But there is a second strong argument,
that should be attractive to designers with zero initial interest
in Python: the features of toVHDL itself.

Basically, toVHDL can make it easier to write VHDL. You note the
difficulties in working with signed/unsigned. Everyday, designers
must be struggling with this. With the backing of toVHDL,
I believe I can make the bold claim that it's all wasted energy.
With intbv's, expressions simply work as you expect. When
you convert to VHDL, the convertor handles all the necessary
castings and resizings. That should be good news.

The remaining question: how large is the public? At some point,
I thought VHDL support was no longer an issue as the whole world
was going to (System)Verilog. For the ASIC world, that may
actually be the case. On the other hand, just some days ago
I received an e-mail from a designer in a major electronics company
with suggestions for toVHDL.

For the FPGA world, I'm getting some feedback (including from this
mailing list) that suggests that the number of VHDL designers
may still be the majority. (I should release toVHDL before
more of them start thinking that Verilog would be a better option :-)).

On the other hand, there is prototype toVHDL function in the
development release, which is probably good enough to get started,
and I'm not getting a lot of feedback on this, so again it
doesn't seem very urgent. Of course, if the purpose is to
attract new users I shouldn't probably expect them to work
with development prototypes.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
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