[myhdl-list] toVHDL

[Thomas H. <th...@ct...>]

Just because I'm curious:  *Why* do we need toVHDL?


I have developed a (very) few FPGA designs in VHDL, I learned it
because it seems to be the standard, and because I have visited one of the
free Xilinx seminars to get started.

My experience was somewhat frustating, and I got the impression that verilog
would have been a better choice.  But I never made the switch.

So, some days ago, I had to start a new small design, in VHDL of course.
Things were frustating again, problems with singed/unsigned interpretation
of signals and other stuff.

Well, I got the first part of the design working eventually.
For fun I thought: this is a good reason to try MyHDL again.
Recoded the main part of the design in MyHDL, simulated it,
it worked fine.  I called toVerilog() on it, had a verilog module,
inserted this as source into my project, and instantiated it in
the top-level VHDL module.  Xilinx ise even has a 'View HDL Instantiation
Template' command that produced the VHDL I needed to insert into the top level.
Synthesized the design and it worked again.

The, I needed a pipelined binary divider.  Xilinx provides a core in the core generator
that generates a netlist for it (as I understand).  Used it and it worked.  OTOH, I thought
it might be fun to design one in MyHDL.  It was fun, doing it with TDD, and after a few iterations
it simulated (in MyHDL) correctly - even had lower pipeline latency than the xilinx one because
of my special restrictions on the inputs; it is not as universal as the xilinx core.
Called toVerilog(), and - whoops - the design again worked in hardware.

So, the question again (which may be very dumb given my limited experience):
Do we really need toVHDL (I think I was one of those originally asking for it,
probably years ago)?

Thanks,
Thomas