Re: [myhdl-list] Need some help expressing my thoughts to myhdl

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:
> Nathan Cain wrote:
> 
>>The split generators was an artifact from a time when this logic was  
>>part of another module.  I agree, this should be cleaned up before  
>>moving to synthesis... but I'm not there yet.
> 
> 
> Ok.
> 
> 
>>That being said, it still doesn't really answer the question of how  
>>to do the byte concatenation...
> 
> 
> Variable part-selects in Verilog are problematic.
> 
> I would avoid the issue altogether by using shifting, like so:
> 
>      cpu_d.next[8:0] = rom
>      cpu_d.next[W:8] = cpu_d.next[W-8:0]
Correction:              cpu_d[W-8:0]
> 
> where W = len(cpu_d).
> 
> Use the counter to decide when to shift, and to detect
> when the cpu_d is ready, all from within a generator
> triggered by a clock edge. This should also create
> efficient hardware.
> 
> Jan
> 


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