Re: [myhdl-list] intbv

[Thomas H. <th...@ct...>]

Christopher L.Felton schrieb:
> By default intbv (similar to int type) is by default signed, just  
> assign it to a negative value.  I believe some care is needed to direct  
> the toVerilog conversion.
> 
> Jan added an example,  
> http://myhdl.jandecaluwe.com/doku.php/cookbook:sinecomp , just for this  
> topic.
> 
> The example shows how to use the intbv as signed value and also shows  
> the synthesis results.
> 
>  From the example sin_z0 = Signal(intbv(0, min=-M-D, max=M+D)) is used  
> to define a signed value with a limited range.
> 
> Also see.
> http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-intbv.html
> http://www.jandecaluwe.com/Tools/MyHDL/manual/conf-features-signed.html

Yes, that did help indeed.  Quoting from the last url you mentioned:

    The Verilog converter handles negative intbv objects by using a signed Verilog representation. Also,
    it automatically performs sign extension and casting to a signed representation when unsigned numbers
    are used in a mixed expression. In this way, it automates a task which is notoriously hard to get
    right in Verilog directly.

I was confused because the tutorial always mentioned this
  Signal(intbv(0)[12:])
to create a 12-bit bus, but it does always create an unsigned signal.

> The following are some simple examples.

[...]

> Note at the end, the bit manipulations don't seem to maintain the  
> sign'ness?  Some one else maybe able to comment on why that is  
> incorrect usage?

Maybe this is a bug?

> Hope that helps.

Thanks,
Thomas