Re: [myhdl-list] intbv

[Christopher L. F. <cf...@uc...>]

By default intbv (similar to int type) is by default signed, just  
assign it to a negative value.  I believe some care is needed to direct  
the toVerilog conversion.

Jan added an example,  
http://myhdl.jandecaluwe.com/doku.php/cookbook:sinecomp , just for this  
topic.

The example shows how to use the intbv as signed value and also shows  
the synthesis results.

 From the example sin_z0 = Signal(intbv(0, min=-M-D, max=M+D)) is used  
to define a signed value with a limited range.

Also see.
http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-intbv.html
http://www.jandecaluwe.com/Tools/MyHDL/manual/conf-features-signed.html

The following are some simple examples.
from myhdl import *

width = 4
# Max is 1 above the actual number, like range
x = intbv(-8, min=-8, max=8)

# Increment and look at the bits
print "Add one to intbv intialized to -8"
print "x: ", bin(x, width), " ", x
for i in range(15):
     x = x + 1
     print "x: ", bin(x, width), " ", x

# Assign negative numbers, remember python, usually reassigning
# references, can't simply assign x = -8.  Note if value
# is greater than 7 or less than -8 get bounds exception
print "\n Assign directly intbv"
for i in range(-8, 8):
     x = intbv(i, min=-8, max=8)
     print "x: ", bin(x, width), " ", x

# Walk through the bit indexes
print "\nWalk through the bits"
for i in range(width):
     x[i] = 1
     print "x: ", bin(x, width), " ", x
     x[i] = 0

# Set all bits to 1
print "\nSet all bits"
for i in range(width):
     x[i] = 1
print "x: ", bin(x, width), " ", x


Note at the end, the bit manipulations don't seem to maintain the  
sign'ness?  Some one else maybe able to comment on why that is  
incorrect usage?

Hope that helps.

On May 16, 2007, at 2:55 AM, Thomas Heller wrote:

> My understanding is that intbv normally represents unsigned integers.
>
> How can I implement signed int arithmetic in MyHDL?
>
> Thanks,
>
> Thomas
>
>
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