Re: [myhdl-list] Need some help expressing my thoughts to myhdl

[Jan D. <ja...@ja...>]

Nathan Cain wrote:

Before going to the heart of the matter, I have a problem
with this code:

>      @always(rst.negedge, state)
>      def StateLogic():
>          if(rst == 0 or state == 0):
>              cpu_ready.next = 1
>              rom_a.next = (cpu_a * bytes)
>          if state != 0:
>              #print "fetching byte %d, %x = %x" % (state, rom_a, rom_d)
>              rom_a.next = rom_a + 1
>              thistop = (top - ((state-1) * 8))
>              #cpu_d.next[thistop:thistop-7] =  rom_d
>              cells[state-1].next = rom_d
>          if(state == bytes):
>              cpu_ready.next = 0

I expect that any synthesis tool would complain about this
as it's not clear how this can be implemented in reliable
hardware.

I would expect that all your logic would be triggered by
the clock. Also, the design seems simple enough so that
everything can be done within a single generator,
both the state (really a counter) and the data operations.

Jan

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