[myhdl-list] Need some help expressing my thoughts to myhdl

[Nathan C. <na...@in...>]

Hello,

I am working on modelling various portions of an SoC we are currently  
developing in myhdl, with the goal of conversion to verilog for  
synthesis.  Currently, I have as part of the design a sort of "rom  
bridge" which allows a cpu core which would normally be running from  
code stored in block ram with a (verilog parameterized) variable  
width bus to run from an off-chip rom with a fixed 8 bit width.  This  
is the myhdl code as it sits today:

from myhdl import *


def RomBridge(
               clk, rst,
               rom_a, rom_d, rom_ce, rom_oe,
               cpu_a, cpu_d, cpu_start, cpu_ready,
               ):

     state = Signal(intbv(0)[7:0]) #idle


     width = len(cpu_d)+1
     bytes = width/8
     top = bytes * 8 - 1

     cells = [];

     for i in range(bytes):
         cells.append(Signal(intbv(0)[7:0]))

     print "Instantiating RomBridge with dwidth %d (bytes %d)" %  
(width, bytes)

     #Watch for cpu_start to go low, and begin state transitioning
     @always(clk.posedge, rst.negedge)
     def TransitionLogic():
         if(rst == 0):
             state.next = 0
         else:
             if (cpu_start == 0 and state <= bytes):
                 state.next = state + 1
             else:
                 state.next = 0

     @always(rst.negedge, state)
     def StateLogic():
         if(rst == 0 or state == 0):
             cpu_ready.next = 1
             rom_a.next = (cpu_a * bytes)
         if state != 0:
             #print "fetching byte %d, %x = %x" % (state, rom_a, rom_d)
             rom_a.next = rom_a + 1
             thistop = (top - ((state-1) * 8))
             #cpu_d.next[thistop:thistop-7] =  rom_d
             cells[state-1].next = rom_d
         if(state == bytes):
             cpu_ready.next = 0


     return instances()


You'll notice that cpu_d never actually gets set.... the commented  
line just above the assignment to cells[state-1] would do what i  
want, but the simulation and synthesis flow chokes on the generated  
verilog. (as it requires an assignment to a non-constant part select  
of a reg! eep!)

After a ToVerilog, the simple addition of a concatenation like  
"assign cpu_d = {cells[0], cells[1], cells[2], cells[3]};" makes for  
a design which passes the module requirements... however, the python  
simulations are non-functional and of course there's the issue of  
having to put that continuous assign back in manually every time....  
and having to manually write code for the specific width being used  
at the moment, instead of having it magic-ed up for me... etc

What I'm looking for is a way to do the assignment to cpu_d at the  
myhdl level, which will simulate correctly in myhdl and ToVerilog up  
some properly simulatable/synthesizable sanity.

Help! :-)

Most everything i've tried either breaks ToVerilog (with less then  
straightforward error messages, heh) or results in verilog with an  
assignment to a non-constant part select.  I understand what I want  
to do, I just can't seem to express it with python code that is  
friendly to myhdl to make my fpga toolchain understand what I want to  
do.

If anyone has a better approach to implementation altogether, I'm  
open to suggestions as well.

Thanks in advance for any assistance anyone can provide!
--Nathan Cain
Inverse Engineering