Re: [myhdl-list] MyHDL and synthesize to non HDL

[<joa...@em...>]

dannoritzer schrieb:
> Have you looked into the toVerilog function?
no, not yet, will have a look at it.
>  I know you don't want to gothat way, just a thought here.
I do not mind going that way, seems natural to me.
>  If you code complies to the restrictions
> for toVerilog, I wonder how difficult it would be create a toC function,
> based on the existing toVerilog code.
>   
I read a similar question from George Pantazopoulos (on 2006/09/26) 
about synthesizability of classes
and Jan did not give much hope for that. In my case, the classes are 
somehow essential
for me. The individual activities would be handled by ISRs triggered by 
interrupt on the
port pin or by a timer. But I'll have a look at toVerilog and see if I 
have a chance.

Joachim