Re: [myhdl-list] MyHDL and synthesize to non HDL

[dannoritzer <dan...@we...>]

Joachim König-Baltes wrote:
> I've used MyHDL to model the 1-wire protocol from dallas
> between a master and a slave, and it was really easy to
> do so although I was a bit skeptical concerning the
> restrictions of standard generators.
> 
> I was even able to write it as an OO model based on classes.
> 
[...]
> 
> Now to my question:
> 
> Is MyHDL suited to synthesize C from the python code?
> 

Have you looked into the toVerilog function? I know you don't want to go
that way, just a thought here. If you code complies to the restrictions
for toVerilog, I wonder how difficult it would be create a toC function,
based on the existing toVerilog code.

Guenter