[myhdl-list] MyHDL and synthesize to non HDL

[<joa...@em...>]

I've used MyHDL to model the 1-wire protocol from dallas
between a master and a slave, and it was really easy to
do so although I was a bit skeptical concerning the
restrictions of standard generators.

I was even able to write it as an OO model based on classes.

As the protocol is rather stable now I'd like to use the
model for synthesizing it, but not into hardware but:

I'd like to use AVR microcontrollers for doing some home automation
with the 1-wire protocol for the communication between them
(because it's simple and electrically uncritical over "long"
distances). I'd like to map it onto different resources inside
the AVRs depending on their capabilities (UART, port, USI) and
have written models for these resources.

The AVRs can be programmed in C rather easily.

Now to my question:

Is MyHDL suited to synthesize C from the python code?

My idea would be as follows: A class instance could model a particular
AVR microcontroller and I could assign ports or an UART to be
used for 1-wire communication (and other purposes). I would then
like to simulate the combination of instances connected to form
a 1-wire network and then synthesize one of the instances to C in
order to generate the program for the flash of the AVR.

Is this somehow possible (I'm willing to dig deep into MyHDL). If
not, what else can I do with the model? If I still have to hand-code
the AVR in C, how can I at least have some advantage of MyHDL in
relation to the C-program?


Joachim