Re: [myhdl-list] Conversion to VHDL - what's new document

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
>>I have finalized a first version of a what's new
>>document for MyHDL 0.6, about VHDL conversion:
>>
>>     http://myhdl.jandecaluwe.com/doku.php/dev:whatsnew:0.6
>>
>>Most features can be tried with 0.6dev2, available from the
>>develpment snapshots page. The development status is here:
>>
>>     http://myhdl.jandecaluwe.com/doku.php/dev:todo:0.6
>>
>>Feedback welcome. Especially if there's something you don't
>>like about it, I'd like to hear it now!
>>
> 
> 
> Nice work, Jan! This is exciting news for me because someone wants a VHDL
> version of my PhoenixSID core. Now they don't have to convert it by hand
> like they wanted to (ouch!) ;-)

Such projects validate the idea to position MyHDL as an IP development
platform, with both Verilog and VHDL output from a single MyHDL source.

> I think doing a VHDL version of the PhoenixSID core would be a good
> real-world test for your VHDL conversion, and can provide some excellent
> feedback.

Definitely.

> The only problem is timing. It's probably going to be a week or two before
> I can really put it to the test.

No problem, there's still a lot of development to do. There may be a new
development release in the mean time. My goal is to have the 0.6 release
ready before the end of the year, though.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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