Re: [myhdl-list] difficulty using itertools with MyHDL

[George P. <ge...@ga...>]

> 
> def bench_1():
> 
>     driver_ats = \
>     """
>     Begin ASCII Timing Spec
>    
>     clk     = ----____----____----____----____
>     rst     = --------________________________
>        
>     End ASCII Timing Spec
>     """   
> 
>     monitor_ats = \
>     """
>     Begin ASCII Timing Spec
> 
>     count_o = X.......0.......1.......2.......
> 
>     End ASCII Timing Spec
>     """
> 
> 
>     sigs['clk'] = Signal(bool(0))
>     sigs['rst'] = Signal(bool(0))
>     sigs['count_o'] = Signal(intbv(0)[4:])
> 
>     dut = ringbuffer(clk     = sigs['clk'],
>                      rst     = sigs['rst'],
>                      count_o = sigs['count_o'])
> 
>     # Manipuate the dut in two stages.
>     # Stage 1: performs setup (eg fills the ringbuffer)
> 
>     # Stage 2: drive inputs and check outputs.
>     #          Tests a boundary case that involves a full ringbuffer.
> 
>     stage1  = filler()
> 
>     driver  = drive_signals_using_ats(driver_ats,  sigs)
>     monitor = check_signals_using_ats(monitor_ats, sigs)
> 
>     stage2  = izip(driver(), monitor())
> 
>     combo = chain(stage1, stage2, stopsim())
> 
>     return combo
> 
> # ---------------------------
> 
> def test():
> 
>     sim = Simulation(bench_1())
>     sim.run()
> 
> 
Just a quick note.. I accidentally mixed a up-counter example and a ringbuffer example here, but the principle is the same

George