Re: [myhdl-list] difficulty using itertools with MyHDL

[George P. <ge...@ga...>]

>
>>> I'd also like to go back to what you actually want to
>>> achieve. Running "in lockstep" in event-driven simulation
>>> is best achieved by waiting on signal changes. This should
>>> be possible using "conventional" simulator usage. Perhaps
>>> there are other ways to achieve what you want, or at
>>> least give more insight in the problem.
>>>   
>>>       
> Hi Jan,
>   
>    I don't have time for a full reply at the moment, but in brief:
>
>    1) I want to run a unit test where there are sequential "stages"
>
>    2) Some of the stages need a driver/monitor pair running "in lockstep".
>       The "driver" manipulates the signals going into the dut.
>       The "monitor" checks the dut outputs.
>
>       My coding efforts in this thread stem from the above points. Can I 
> help you further by elaborating on any of my ideas? I'm confident you 
> will come to an understanding soon.
>
> Thanks,
> George
>
>   
Hi Jan,

   To elaborate, for a unit test I wish to parse a pair of ASCII Timing 
Spec (ATS) blocks into a driver/monitor combo. However before doing that 
I want to set up the device under test using a separate generator (in 
this example it fills up the ringbuffer to set up a border case). I'd 
like to be able to reuse this setup generator filler() across multiple 
unit tests.

I'm still tweaking the syntax and usage of the ASCII Timing Spec 
(feedback would be helpful here), but what I want looks something like this:

The ASCII Timing Spec specifies the signal states at each timestep, not 
just at edges. So I think my driver loop would involve doing something 
like yield delay(1) between setting each signal to its .next value. 
Likewise, the monitor would yield delay(1) between each iteration of 
checking the signals (according to the ATS):

def bench_1():

    driver_ats = \
    """
    Begin ASCII Timing Spec
   
    clk     = ----____----____----____----____
    rst     = --------________________________
       
    End ASCII Timing Spec
    """   

    monitor_ats = \
    """
    Begin ASCII Timing Spec

    count_o = X.......0.......1.......2.......

    End ASCII Timing Spec
    """


    sigs['clk'] = Signal(bool(0))
    sigs['rst'] = Signal(bool(0))
    sigs['count_o'] = Signal(intbv(0)[4:])

    dut = ringbuffer(clk     = sigs['clk'],
                     rst     = sigs['rst'],
                     count_o = sigs['count_o'])

    # Manipuate the dut in two stages.
    # Stage 1: performs setup (eg fills the ringbuffer)

    # Stage 2: drive inputs and check outputs.
    #          Tests a boundary case that involves a full ringbuffer.

    stage1  = filler()

    driver  = drive_signals_using_ats(driver_ats,  sigs)
    monitor = check_signals_using_ats(monitor_ats, sigs)

    stage2  = izip(driver(), monitor())

    combo = chain(stage1, stage2, stopsim())

    return combo

# ---------------------------

def test():

    sim = Simulation(bench_1())
    sim.run()


Let me know what else you might need to understand what I want to do. 
The ATS is intended to make unit tests more fun to write and maintain.

Thanks,
George