Re: [myhdl-list] 0.6dev1

[George P. <ge...@ga...>]

>
> Yes, I think VHDL conversion support may position MyHDL in a new way:
> a powerful IP development platform, that can generate equivalent Verilo=
g
> and VHDL from the same source base.

Indeed! And I think the ASCII Port Spec and ASCII Timing Spec from MyHDL
Booster will fit in nicely...

>> But also, there are many useful cores on
>> opencores that are VHDL, and I'd love to try integrating them with MyH=
DL
>> hardware modules. Is there a "User-defined VHDL" feature that will hel=
p
>> wrap VHDL modules?
>
> __toVHDL__ support is still to do. (I guess __toVerilog__ would current=
ly
> work with the VHDL conversion however :-)) But that should be easy.
> However, I think VHDL will require something more, as components that y=
ou
> instantiate also have to be declared before. So probably there will als=
o
> have to be way to specify user-defined declarations.
>

:) As usual, I think what would help is if I tried interoperating with a
VHDL module from opencores and then letting you know how it went. I'm
still working on wrapping Verliog modules, though ;-)



--=20
George Pantazopoulos
http://www.gammaburst.net