Re: [myhdl-list] 0.6dev1

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

> Jan, this is awesome news! My friends were impressed that I can now 
> generate Verilog or VHDL.

Yes, I think VHDL conversion support may position MyHDL in a new way:
a powerful IP development platform, that can generate equivalent Verilog
and VHDL from the same source base.

> But also, there are many useful cores on 
> opencores that are VHDL, and I'd love to try integrating them with MyHDL 
> hardware modules. Is there a "User-defined VHDL" feature that will help 
> wrap VHDL modules?

__toVHDL__ support is still to do. (I guess __toVerilog__ would currently
work with the VHDL conversion however :-)) But that should be easy.
However, I think VHDL will require something more, as components that you
instantiate also have to be declared before. So probably there will also
have to be way to specify user-defined declarations.

Jan

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