Re: [myhdl-list] 0.6dev1

[George P. <ge...@ga...>]

Jan Decaluwe wrote:
> Hi:
>
> I'll be taking a few day off, and before that I wanted to
> release the current development status of MyHDL's assault
> on VHDL. Hence, 0.6dev1. See:
>
> http://myhdl.jandecaluwe.com/doku.php/snapshots#snapshots
> http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.6
> http://myhdl.jandecaluwe.com/doku.php/todo:0.6
>
> Regards, Jan
>   
Jan, this is awesome news! My friends were impressed that I can now 
generate Verilog or VHDL. But also, there are many useful cores on 
opencores that are VHDL, and I'd love to try integrating them with MyHDL 
hardware modules. Is there a "User-defined VHDL" feature that will help 
wrap VHDL modules?

Keep up the inspired work :)
George