[myhdl-list] Experimental demo using classes, ASCII Port Spec and Verilog output

[George P. <ge...@ga...>]

Hey all,

   Here's what I'm working on currently, It's still evolving, and my 
goal is to cleanly support a WISHBONE system, the Python and MyHDL way:

http://myhdl.jandecaluwe.com/doku.php/users:george_pantazopoulos:demo_1

Feedback welcome.
I'd recommend starting at the bottom and working your way up :)

George