Re: [myhdl-list] Visual Timing Specification for unit testing - complete example

[George P. <ge...@ga...>]

On Tue, October 3, 2006 4:42 am, G=FCnter Dannoritzer wrote:
> George Pantazopoulos wrote:
>> All,
>>     I've come up with a solution that made writing unit tests massivel=
y
>> more fun and less tedious and error-prone for me.
>>
>> I've found a way to make an easily human-readable ascii timing diagram=
.
>> However, this timing diagram is special because the very same diagram
>> can be parsed and used to drive a MyHDL unit test.
>
> Hi George,
>
> That is a good idea. I briefly looked over the code and saw that you ar=
e
> doing the parsing yourself.
>

> I wonder whether in the long run using a parser package would help for
> the code not to get too complex. I found this PyParsing package a while
> ago http://pyparsing.wikispaces.com/ that can be used very flexible for
> all kinds of parsing.
>
>  > I have some improvements planned (such as support for negedges).
>> Feedback welcome.
>>
>
> I ran over such a tool a while ago -- though not for MyHDL :) --. It di=
d
> parse the timing data from an ASCII file. I googled for it, but have no=
t
> found it yet. I just wonder whether there exists already some common
> character set to specify signal data. Maybe that would allow to use it
> to use output from other tools in MyHDL? Just a thought.
>

I think those are good suggestions Guenter, thanks. If you come across
that tool, drop me a line.

Thanks,
George

--=20
George Pantazopoulos
http://www.gammaburst.net