Re: [myhdl-list] Visual Timing Specification for unit testing - complete example
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Re: [myhdl-list] Visual Timing Specification for unit testing - complete example
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From: George P. <ge...@ga...> - 2006-10-05 16:47:43
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On Thu, October 5, 2006 11:36 am, Thomas Heller wrote: > George Pantazopoulos schrieb: >> Timing: >> ------- >> >> When driving signals with the VTS, assume that the signal >> will be valid at the clock edge. >> >> When checking signals with the VTS, the signal value checked for >> must be valid by the time the corresponding edge arrives. >> >> >> Condensed Timing Spec >> --------------------- >> >> The result of parsing a Visual Timing Spec is a Condensed Timing >> Spec. >> Its format is similar to the VTS, except that it's not restricted = to >> ASCII and contains only the data for each clock edge, with no >> padding. >> >> The CTS is to be passed as input to the actual driver and monitor >> functions. >> >> TODO: >> ----- >> >> TODO: Make it possible to optionally specify negedges too. Eg: >> edges =3D "|0....v.....|1....v.....|2....v...." >> Where 'v' denotes a negedge >> > > Would not '/' for positive edges and '\' for negative edges look nicer? > > edges =3D r"/0....\...../1....\...../2....\...." > or > edges =3D r"/0----\_____/1----\_____/2----\ " > > Thomas > Yeah, thats great! Thanks a lot, Tom. George --=20 George Pantazopoulos http://www.gammaburst.net |
