Re: [myhdl-list] Visual Timing Specification for unit testing - complete example

[Thomas H. <th...@py...>]

George Pantazopoulos schrieb:
>     Timing:
>     -------
>    
>     When driving signals with the VTS, assume that the signal
>     will be valid at the clock edge.
>    
>     When checking signals with the VTS, the signal value checked for
>     must be valid by the time the corresponding edge arrives.
>      
>      
>     Condensed Timing Spec
>     ---------------------
>    
>     The result of parsing a Visual Timing Spec is a Condensed Timing Spec.
>     Its format is similar to the VTS, except that it's not restricted to
>     ASCII and contains only the data for each clock edge, with no padding.
>    
>     The CTS is to be passed as input to the actual driver and monitor
>     functions.  
> 
>     TODO:
>     -----
>    
>     TODO: Make it possible to optionally specify negedges too. Eg:
>     edges  =   "|0....v.....|1....v.....|2....v...."
>     Where 'v' denotes a negedge
>    

Would not '/' for positive edges and '\' for negative edges look nicer?

      edges =   r"/0....\...../1....\...../2....\...."
or
      edges =   r"/0----\_____/1----\_____/2----\    "

Thomas