Re: [myhdl-list] Dream Mux (still a dream for now)

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

> 
> How difficult would it be to enhance the Verilog converter so it accepts 
> dict lookups in generators?
> 
> I really want to have the ability to do this:
> 
> @always(sigs['clk'].posedge)
> def Proc():
>    
>     sigs['dat'].next = 0
> 

George:

To meaningfully the assess the difficulty of this I believe
we should move from examples (which are useful to get the ball
rolling) to a comprehensive spec of what really is required.

For example, the example above would require read lookup
based on a constant key.

The first example you posted would require much more:
- read lookup on a loop variable key
- support for the keys() method of dicts, used in a for-loop
- I understand that because of readibility, you would want to
map the for-loop to a Verilog loop in the output

Of course, there are many more things that can be done
with dicts and that are potentially useful in modeling.
Before we know what should be supported, what not, and how
it should map to Verilog if applicable, little can be said
about implementation difficulty.

Discussing about a spec will make it possible to understand
the issues better, and perhaps even come up with a better
solution for what you want to achieve.

Best regards,

Jan

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